Design, Simulation and Testing of a High Speed Low Power 15-4 Compressor for High Speed Multiplication Applications
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4579839/4579840/04579939.pdf?arnumber=4579939
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters;IET Computers & Digital Techniques;2022-11-28
2. An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending;Frontiers of Information Technology & Electronic Engineering;2022-06
3. Optimized Image Multiplication with Approximate Counter Based Compressor;Computers, Materials & Continua;2022
4. Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication;IET Computers & Digital Techniques;2020-12-09
5. Energy-Efficient Differential Spin Hall MRAM-Based 4-2 Magnetic Compressor;IEEE Transactions on Magnetics;2020-01
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