Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed

Author:

A Arul ORCID,M Kathirvelu

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference27 articles.

1. High-speed hybrid-logic full adder using high-performance 10-T XOR–XNOR cell;Kandpal;IEEE Trans. Very Large Scale Integr. Syst.,2020

2. Design of a scalable low-power 1-bit hybrid full adder for fast computation;Hasan;IEEE Trans. Circuits Syst. II: Express Briefs,2020

3. A high‐performance full swing 1‐bit hybrid full adder cell, IET Circuits;Hussain;Devices & Systems,2021

4. Hybrid logical effort for hybrid logic style full adders in multistage structures;Basireddy;IEEE Trans. Very Large Scale Integr. Syst.,2019

5. Gate diffusion input technique based full swing and scalable 1-bit hybrid full adder for high performance applications, Engineering Science and Technology;Hasan;Int. J.,2020

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