Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures-Reference-Cited by-同舟云学术

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Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures

Published:2019-05 Issue:5 Volume:27 Page:1138-1147
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

basireddy hareesh-reddy,challa Karthikeya,Nikoubin Tooraj^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8698469/08626142.pdf?arnumber=8626142

Cited by 41 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A comprehensive analysis of ultra low power GNRFET based 20T hybrid full adder for computing applications;Physica Scripta;2024-07-05

2. Design of Low Power and High Speed 1-bit Full Adder for DSP Applications;2024 International Conference on Advancements in Power, Communication and Intelligent Systems (APCI);2024-06-21

3. A novel low-power full swing hybrid full adder-based 7:3 counter for MBW multiplier;Sādhanā;2024-05-30

4. Comparative analysis of hybrid logic style full adders in multistage structures;AIP Conference Proceedings;2024

5. Design a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency and high-speed;Analog Integrated Circuits and Signal Processing;2023-12-29

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