A novel low-power full swing hybrid full adder-based 7:3 counter for MBW multiplier
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Publisher
Springer Science and Business Media LLC
Link
https://link.springer.com/content/pdf/10.1007/s12046-024-02537-5.pdf
Reference21 articles.
1. Shahzad A and Yinan K 2015 Design of an algorithmic Wallace multiplier using high speed counters. In: Proceedings of the Tenth International Conference on Computer Engineering & Systems (ICCES), Cairo. Egypt, pp. 133–138. https://doi.org/10.1109/ICCES.2015.7393033
2. Khurshid B and Mir R N 2015 High efficiency generalized parallel counters for Xilinx FPGAs. In: Proceedings of the IEEE 22nd International Conference on High Performance Computing (HiPC), pp. 40–46. https://doi.org/10.1109/HiPC.2015.41
3. Fritz C and Fam A T 2017 Fast binary counters based on symmetric stacking 2017. IEEE Trans. Very Large Scale Integr. Syst. 25: 2971–2975. https://doi.org/10.1109/TVLSI.2017.2723475
4. Mukherjee B and Ghosal A 2019 Design of a low power, double throughput CCGDI based radix-4 MBW multiplier and accumulator (MAC) unit for on-chip RISC processors of MEMS sensor. J. Micromech. Microeng. 29: 064003. https://doi.org/10.1088/1361-6439/ab1504
5. Mukherjee B and Ghosal A 2019 Low power dynamic voltage scaling CCGDI based Radix-4 MBW multiplier using parallel HA and FA counters for on-chip filter applications. Sadhana Acad. Proc. Eng. Sci. 5 article id: 0119. https://doi.org/10.1007/s12046-020-01340-2
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