Design of an algorithmic Wallace multiplier using high speed counters
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7386534/7392993/07393033.pdf?arnumber=7393033
Cited by 25 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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3. High-Speed Grouping and Decomposition Multiplier for Binary Multiplication;Electronics;2022-12-16
4. Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters;IET Computers & Digital Techniques;2022-11-28
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