Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications-Reference-Cited by-同舟云学术

Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications

Published:2020-05-12 Issue:1 Volume:45 Page:
ISSN:0256-2499
Container-title:Sādhanā
language:en
Short-container-title:Sādhanā

Author:

Mukherjee Biswarup^ORCID,Ghosal Aniruddha

Publisher

Springer Science and Business Media LLC

Subject

Multidisciplinary

Link

https://link.springer.com/content/pdf/10.1007/s12046-020-01340-2.pdf

Reference24 articles.

1. Kumar M A, Rao O R, Dileep M, Reddy C V P Rand Mani K P 2016 Performance Evaluation of Different Multipliers in VLSI using VHDL. International Journal of Advanced Research in Computer and Communication Engineering 5: 6–11

2. Lamba Band Sharma A 2018 A review paper on different multipliers based on their different performance parameters In: Proceedings of the 2nd International Conference on Inventive Systems and Control (ICISC) : pp. 324–327

3. Carbognani F, Buergin F, Felber N, Kaeslin H and Fichtner W 2008 A low-power transmission-gate-based 16-bit multiplier for digital hearing aids. Analog Integrated Circuit and Signal Processing 56: 5–12

4. Xue H, Patel R, Boppana N V V K and Ren S 2018 Low-power-delay-product radix-4 8*8 Booth multiplier in CMOS. Electronics Letter 54: 344–346

5. Colón-Bonet G andWinterrowd P 2008 Multiplier Evolution: A Family of Multiplier VLSI Implementations. The Computer Journal 51: 585–594

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A novel low-power full swing hybrid full adder-based 7:3 counter for MBW multiplier;Sādhanā;2024-05-30

2. FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing;Journal of Circuits, Systems and Computers;2024-04-10