基于特定最低有效位动态阈值碳纳米管场效应晶体管的高效优化近似栅极扩散输入全加器-Reference-Cited by-同舟云学术

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基于特定最低有效位动态阈值碳纳米管场效应晶体管的高效优化近似栅极扩散输入全加器

Published:2023-04 Issue:4 Volume:24 Page:599-616
ISSN:2095-9184
Container-title:Frontiers of Information Technology & Electronic Engineering
language:en
Short-container-title:Front Inform Technol Electron Eng

Author:

Sadeghi Ayoub^ORCID,Ghasemi Razieh,Ghasemian Hossein^ORCID,Shiri Nabiollah

Publisher

Zhejiang University Press

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing

Link

https://link.springer.com/content/pdf/10.1631/FITEE.2200077.pdf

Reference41 articles.

1. Abdul Hadi MF, Hussin H, Soin N, 2022. The impact of variation in diameter and dielectric materials of the CNT field-effect transistor. ECS J Sol State Sci Technol, 11(2):023002. https://doi.org/10.1149/2162-8777/ac4ffc

2. Abiri E, Darabi A, Salehi MR, et al., 2020. Optimized gate diffusion input method-based reversible magnitude arithmetic unit using non-dominated sorting genetic algorithm II. Circ Syst Signal Process, 39(9):4516–4551. https://doi.org/10.1007/s00034-020-01382-1

3. Ben-Jamaa MH, Mohanram K, de Micheli G, 2011. An efficient gate library for ambipolar CNTFET logic. IEEE Trans Comput-Aided Des Integr Circ Syst, 30(2):242–255. https://doi.org/10.1109/tcad.2010.2085250

4. Cardenas JA, Lu SH, Williams NX, et al., 2021. In-place printing of flexible electrolyte-gated carbon nanotube transistors with enhanced stability. IEEE Electron Dev Lett, 42(3):367–370. https://doi.org/10.1109/led.2021.3055787

5. Cho G, Lombardi F, 2016. Design and process variation analysis of CNTFET-based ternary memory cells. Integration, 54:97–108. https://doi.org/10.1016/j.vlsi.2016.02.003

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1. Optimized Gate Sizing for Improved Performance and Power Efficiency in Adder Circuits;Proceedings of the 6th International Conference on Information Technologies and Electrical Engineering;2023-11-03

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