Design of an algorithmic Wallace multiplier using high speed counters-Reference-Cited by-同舟云学术

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Design of an algorithmic Wallace multiplier using high speed counters

Published:2015-12 Issue: Volume: Page:
ISSN:
Container-title:2015 Tenth International Conference on Computer Engineering & Systems (ICCES)
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Author:

Asif Shahzad,Kong Yinan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7386534/7392993/07393033.pdf?arnumber=7393033

Cited by 33 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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