Lateral current-constriction in vertical devices using openings in buried lattices of metallic discs
Author:
Publisher
AIP Publishing
Subject
Physics and Astronomy (miscellaneous)
Link
http://aip.scitation.org/doi/pdf/10.1063/1.120141
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1. A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks;2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems;2008-10
2. A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates;26th IEEE VLSI Test Symposium (vts 2008);2008-04
3. A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates;2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems;2006-10
4. Characteristics of electron transport through vertical double-barrier quantum-dot structures: Effects of symmetric and asymmetric variations of the lateral confinement potentials;Physical Review B;2002-11-21
5. Carrier dynamics around nano-scale Schottky contacts: a femtosecond near-field study;Applied Surface Science;2002-05
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