Author:
Goparaju Manoj Kumar,Tragoudas Spyros
Cited by
4 articles.
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1. Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms;ACM Journal on Emerging Technologies in Computing Systems;2014-04
2. A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate;2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems;2011-10
3. Probabilistic metric of gate logical fault occurrence due to manufacturing inaccuracy of threshold logic gates for efficient testing;2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era;2009-04
4. A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks;2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems;2008-10