Author:
Dechu Sandeep,Goparaju Manoj,Tragoudas Spyros
Cited by
7 articles.
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1. A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-07
2. Threshold Logic in a Flash;2019 IEEE 37th International Conference on Computer Design (ICCD);2019-11
3. Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-09
4. A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate;2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems;2011-10
5. Probabilistic metric of gate logical fault occurrence due to manufacturing inaccuracy of threshold logic gates for efficient testing;2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era;2009-04