Optimal Ge/SiGe nanofin geometries for hole mobility enhancement: Technology limit from atomic simulations
Author:
Affiliation:
1. School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, USA
2. School of Materials Engineering and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907, USA
Funder
National Science Foundation (NSF)
Semiconductor Research Corporation (SRC)
Publisher
AIP Publishing
Subject
General Physics and Astronomy
Link
http://aip.scitation.org/doi/pdf/10.1063/1.4919091
Reference44 articles.
1. Academic and industry research progress in germanium nanodevices
2. Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates
3. Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS
4. High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture
5. High Hole-Mobility Strained-$\hbox{Ge/Si}_{0.6} \hbox{Ge}_{0.4}$ P-MOSFETs With High-K/Metal Gate: Role of Strained-Si Cap Thickness
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. New strategies for producing defect free SiGe strained nanolayers;Scientific Reports;2018-02-13
2. Publisher's Note: “Optimal Ge/SiGe nanofin geometries for hole mobility enhancement: Technology limit from atomic simulations” [J. Appl. Phys. 117, 174312 (2015)];Journal of Applied Physics;2015-07-07
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