Academic and industry research progress in germanium nanodevices

Author:

Pillarisetty Ravi

Publisher

Springer Science and Business Media LLC

Subject

Multidisciplinary

Reference52 articles.

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2. Ghani, T. et al. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. Tech. Digest IEEE Electron Devices Meet. 11.6.1–11.6.3 (IEEE, 2003).

3. Mistry, K. et al. A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. Tech. Digest IEEE Electron Devices Meet. 247–250 (IEEE, 2007).

4. Kim, D. & Del Alamo, J. Scaling behavior of In0.7Ga0.3As HEMTs for logic. Tech. Digest IEEE Electron Devices Meet. 837–841 (IEEE, 2006).

5. Hudait, M. et al. Heterogeneous integration of enhancement mode In0.7Ga0.3As quantum well transistor on silicon substrate using thin (< 2 μm) composite buffer architecture for high-speed and low-voltage (0.5 V) logic applications. Tech. Digest IEEE Electron Devices Meet. 625–628 (IEEE, 2007).

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