Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions-Reference-Cited by-同舟云学术

Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions

Published:2016-03-21 Issue:4 Volume:16 Page:2418-2425
ISSN:1530-6984
Container-title:Nano Letters
language:en
Short-container-title:Nano Lett.

Author:

Wu Jun¹,Babadi Aein Shiri¹,Jacobsson Daniel¹,Colvin Jovana¹,Yngman Sofie¹,Timm Rainer¹,Lind Erik¹,Wernersson Lars-Erik¹

Affiliation:

1. Electrical and Information Technology, ‡Solid State Physics, and §Synchrotron Radiation Research, Lund University, P.O. Box 118, SE-221 00 Lund, Sweden

Funder

Vetenskapsrådet

Crafoordska Stiftelsen

Knut och Alice Wallenbergs Stiftelse

Stiftelsen för Strategisk Forskning

Publisher

American Chemical Society (ACS)

Subject

Mechanical Engineering,Condensed Matter Physics,General Materials Science,General Chemistry,Bioengineering

Link

https://pubs.acs.org/doi/pdf/10.1021/acs.nanolett.5b05253

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4. Extraction of virtual-source injection velocity in sub-100 nm III–V HFETs

5. Vertical nanowire InGaAs MOSFETs fabricated by a top-down approach

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