In Situ SiO2 Passivation of Epitaxial (100) and (110)InGaAs by Exploiting TaSiOx Atomic Layer Deposition Process-Reference-Cited by-同舟云学术

In Situ SiO2 Passivation of Epitaxial (100) and (110)InGaAs by Exploiting TaSiOx Atomic Layer Deposition Process

Published:2018-11-01 Issue:11 Volume:3 Page:14567-14574
ISSN:2470-1343
Container-title:ACS Omega
language:en
Short-container-title:ACS Omega

Author:

Hudait Mantu K.¹^ORCID,Clavel Michael B.¹^ORCID,Liu Jheng-Sin¹,Bhattacharya Shuvodip¹

Affiliation:

1. Advanced Devices & Sustainable Energy Laboratory (ADSEL), Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, Virginia 24061, United States

Funder

Division of Electrical, Communications and Cyber Systems

Publisher

American Chemical Society (ACS)

Subject

General Chemical Engineering,General Chemistry

Link

http://pubs.acs.org/doi/pdf/10.1021/acsomega.8b02314

Reference36 articles.

1. Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications

2. Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

3. Radosavljevic, M.; Chu-Kung, B.; Corcoran, S.; Hudait, M. K.; Dewey, G.; Fastenau, J. M.; Kavalieros, J.; Liu, W. K.; Lubyshev, D.; Metz, M.; Millard, K.; Rachmady, W.; Shah, U.; Chau, R. Advanced High-K Gate Dielectric for High-Performance Short-Channel In0.7Ga0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications. IEDM Technical Digest, 2009; pp 319–322.

4. Radosavljevic, M.; Dewey, G.; Fastenau, J. M.; Kavalieros, J.; Kotlyar, R.; Chu-Kung, B.; Liu, W. K.; Lubyshev, D.; Metz, M.; Millard, K.; Mukherjee, N.; Pan, L.; Pillarisetty, R.; Rachmady, W.; Shah, U.; Chau, R. Non-planar, Multi-gate InGaAs Quantum Well Field Effect Transistors With High-k Gate Dielectric and Ultra-scaled Gate-to-drain/Gate-to-source Separation for Low Power Logic Applications. IEDM Technical Digest, 2010; pp 126–129.

5. Radosavljevic, M.; Dewey, G.; Basu, D.; Boardman, J.; Chu-Kung, B.; Fastenau, J. M.; Kabehie, S.; Kavalieros, J.; Le, V.; Liu, W. K.; Lubyshev, D.; Metz, M.; Millard, K.; Mukherjee, N.; Pan, L.; Pillarisetty, R.; Rachmady, W.; Shah, U.; Then, H. W.; Chau, R. Electrostatics Improvement in 3-D Tri-gate Over Ultra-Thin Body Planar InGaAs Quantum Well Field Effect Transistors with High-K Gate Dielectric and Scaled Gate-to-Drain/Gate-to-Source Separation. IEDM Technical Digest, 2011; pp 765–768.

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Surface Orientated < 100 > , < 110 > , and < 111 > Silicon-based Double-Gate Tunnel-FET for Linearity and Analog/RF Performance Analysis;Silicon;2022-11-23

2. Probing crystallographic orientation-specific carrier lifetimes in epitaxial Ge/AlAs and InGaAs/InP heterostructures;Materials Advances;2022

3. Atomic layer deposited tantalum silicate on crystallographically-oriented epitaxial germanium: interface chemistry and band alignment;Materials Advances;2022

4. Insight into high temperature performance of magnetron sputtered Si-Ta-C-(N) coatings with an ion-implanted interlayer;Applied Surface Science;2021-03

5. Characteristics of In0.7Ga0.3As MOS Capacitors Obtained using Hydrochloric Acid Treatment, Ammonium Sulfide Passivation, Methanol Treatment, and Forming Gas Annealing;ECS Journal of Solid State Science and Technology;2019