1. Double gate strained-Ge heterostructure tunneling FET (TFET) with record high drive current and <60 mV/dec subthreshold slope;T Krishnamohan;IEDM Tech. Dig,2008
2. Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance;F Mayer;IEDM Tech. Dig,2008
3. Modeling of High-Performance p-Type III-V Heterojunction Tunnel FETs;J Knoch;IEEE Electron Device Letters,2010
4. 1D broken-gap tunnel transistor with MOSFET-like on-currents and sub-60 mV/dec subthreshold swing;S O Koswatta;IEDM Tech. Dig,2009
5. Electrical performance of InAs/GaAs0.1Sb0.9 heterostructure junctionless TFET with dual-material gate and Gaussian-doped source;H Xie;Semiconductor Science and Technology,2020