Affiliation:
1. Raytheon Integrated Defense Systems, 362 Lowell Street, Andover, MA 01810, USA
Abstract
Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.
Subject
General Physics and Astronomy,General Engineering,General Mathematics
Reference41 articles.
1. Advanced Packaging: The Redistributed Chip Package
2. Thompson J Tepolt G Mueller LRA Langdo T Gauthier D& Smith B.. 2011 Embedded package wafer bow elimination techniques. IEEE 61st Electronic Components and Technology Conference (ECTC) Lake Buena Vista FL 31 May–3 June pp. 55–58. Piscataway NJ: IEEE. (doi:10.1109/ECTC.2011.5898491).
3. Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection
4. Bonding for 3-D Integration of Heterogeneous Technologies and Materials
Cited by
76 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献