Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

Author:

Kazior Thomas E.1

Affiliation:

1. Raytheon Integrated Defense Systems, 362 Lowell Street, Andover, MA 01810, USA

Abstract

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

Publisher

The Royal Society

Subject

General Physics and Astronomy,General Engineering,General Mathematics

Reference41 articles.

1. Advanced Packaging: The Redistributed Chip Package

2. Thompson J Tepolt G Mueller LRA Langdo T Gauthier D& Smith B.. 2011 Embedded package wafer bow elimination techniques. IEEE 61st Electronic Components and Technology Conference (ECTC) Lake Buena Vista FL 31 May–3 June pp. 55–58. Piscataway NJ: IEEE. (doi:10.1109/ECTC.2011.5898491).

3. Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

4. Bonding for 3-D Integration of Heterogeneous Technologies and Materials

Cited by 71 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Minimizing die fracture in 3DIC die integration;Journal of Micro/Nanopatterning, Materials, and Metrology;2024-01-02

2. Interconnects in a Multi-Layer Polymer-on-Si 50-GHz Packaging Technology;2023 16th International Conference on Advanced Technologies, Systems and Services in Telecommunications (TELSIKS);2023-10-25

3. Approaches to Heterogeneous Integration for Millimeter-Wave Applications;Journal of the Russian Universities. Radioelectronics;2023-09-29

4. Artificial nanophotonic neuron with internal memory for biologically inspired and reservoir network computing;Neuromorphic Computing and Engineering;2023-09-01

5. Floquet engineering-based frequency demodulation method for wireless THz short-range communications;Physica Scripta;2023-08-21

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线,采集、加工和组织学术论文而形成的新型学术文献查询和分析系统,可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容,当前同舟云学术共收录了国内外主流学术期刊6万余种,收集的期刊论文及会议论文总量共计约1.5亿篇,并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询!咨询电话:010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号  京ICP备18003416号-3