Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low Power-Reference-Cited by-同舟云学术

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Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low Power

Published:2018-12-01 Issue:4 Volume:14 Page:548-557
ISSN:1546-1998
Container-title:Journal of Low Power Electronics
language:en
Short-container-title:Journal of Low Power Electronics

Author:

Sasipriya P.,Bhaaskaran V.S. Kanchana

Publisher

American Scientific Publishers

Subject

Electrical and Electronic Engineering

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications;Microprocessors and Microsystems;2024-04

2. Energy-Efficient circuits with improved diode free adiabatic logic design methodology;Ain Shams Engineering Journal;2022-11

3. Design and Evaluation of Clocked Differential Adiabatic Logic Families for Low Power Applications;International Journal of Electronics;2021-09-05

4. Design and analysis of CCDAL based wallace multiplier for power optimization;1ST INTERNATIONAL CONFERENCE ON ADVANCES IN SIGNAL PROCESSING, VLSI, COMMUNICATIONS AND EMBEDDED SYSTEMS: ICSVCE-2021;2021

5. Design of energy efficient carry lookahead adder using novel CSIPGL adiabatic logic circuit;Journal of Physics: Conference Series;2020-12-01

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