Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications-Reference-Cited by-同舟云学术

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Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications

Published:2024-04 Issue: Volume:106 Page:105036
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Gundavarapu Vishal,Gowtham P.,Anita Angeline A.,Sasipriya P.^ORCID

Publisher

Elsevier BV

Reference23 articles.

1. Compressor based hybrid approximate multiplier architectures with efficient error correction logic;Uppugunduru;Comput. Electr. Eng.,2022

2. Signed binary multiplication technique;Booth;Q.J. Mech. Appl. Math.,1951

3. Generalized low-error area-efficient fixed-width multipliers;Van and;IEEE Trans. Circuits Syst. I, Reg. Papers,2005

4. Low-power high-accuracy fixed-width radix-8 Booth multiplier using probabilistic estimation technique;Bhusare;J. Circuits, Syst. Comput.,2017

5. Approximate multipliers based on a novel unbiased approximate 4-2 compressor;Fang;Integration,2021

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