Design and analysis of CCDAL based wallace multiplier for power optimization

Author:

Dhruva P.,Narender M.,Rohith J.,Singh Sangeeta

Publisher

AIP Publishing

Reference14 articles.

1. S. M. Qasim, M. S. BenSaleh and A. M. Obeid, “Efficient FPGA implementation of microprogram control unit based FIR filter using Xilinx and Synopsys tools,” Proc. of Synopsys Users Group Conference (SNUG), Silicon Valley, USA, pp. 1-14, March 2012.

2. S. M. Qasim, A. A. Telba and A. Y. AlMazroo, “FPGA design and implementation of matrix multiplier architectures for image and signal processing applications,” Int. J. Comp. Sci. Network Security, Vol. 10, No. 2, pp. 168-176, Feb. 2010.

3. Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)

4. P. Sasipriya and V. S. K. Bhaskaran, Design and Analysis of Clocked CMOS Differential Adiabatic Logic(CCDAL) for Low Power, 2018.

5. Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application

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