Analytical model for the drain and gate currents in silicon nanowire and nanosheet MOS transistors valid between 300 and 500 K

Abstract

AbstractThis work presents an analytical model for the drain and gate currents of silicon nanowire and nanosheet MOS transistors valid in all operating regions in the temperature range from 300 to 500 K. Analytical models for the tunneling components as well as for the reversely biased drain‐to‐channel PN junction are presented. Also, the models accounting for the necessary modifications in the silicon physical quantities for high‐temperature operation, such as the maximum carrier mobility, the bandgap, and the intrinsic carrier concentration, are presented. The proposed model uses a single set of parameters, extracted at room temperature, to describe the high‐temperature operation of silicon nanowire MOSFETs. The model is validated with comparisons between modeled and experimental results for devices with different fin widths and operating temperatures, with good agreement.