Modeling Junctionless Field-Effect Transistors
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Publisher
Wiley
Link
http://onlinelibrary.wiley.com/wol1/doi/10.1002/9781119523543.ch8/fullpdf
Reference78 articles.
1. Physical insights into the nature of gate-induced drain leakage in ultrashort channel nanowire FETs;Sahay;IEEE Trans. Electron Devices,2017
2. A novel gate-stack-engineered nanowire FET for scaling to the sub-10-nm regime;Sahay;IEEE Trans. Electron Devices,2016
3. Spacer design guidelines for nanowire FETs from gate-induced drain leakage perspective;Sahay;IEEE Trans. Electron Devices,2017
4. Insight into lateral band-to-band-tunneling in nanowire junctionless FETs;Sahay;IEEE Trans. Electron Devices,2016
5. Controlling L-BTBT and volume depletion in nanowire JLFETs using core-shell architecture;Sahay;IEEE Trans. Electron Devices,2016
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1. Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications;ECS Journal of Solid State Science and Technology;2023-09-01
2. Complete depletion area in SOI junctionless FETs by multiple buried P-type pockets;The European Physical Journal Plus;2023-06-14
3. Investigation of the Direct Source to Drain Tunneling in 5 nm Nanotube Junctionless Field Effect Transistor;2023 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS);2023-04-05
4. Realization of Double‐Gate Junctionless Field Effect Transistor Depletion Region for 6 nm Regime with an Efficient Layer;physica status solidi (a);2022-08-15
5. Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer;physica status solidi (a);2022-03-29
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