A Novel Gate-Stack-Engineered Nanowire FET for Scaling to the Sub-10-nm Regime-Reference-Cited by-同舟云学术

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A Novel Gate-Stack-Engineered Nanowire FET for Scaling to the Sub-10-nm Regime

Published:2016-12 Issue:12 Volume:63 Page:5055-5059
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Sahay Shubham^ORCID,Kumar Mamidala Jagadesh^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/7739934/07723900.pdf?arnumber=7723900

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