Investigation of the Direct Source to Drain Tunneling in 5 nm Nanotube Junctionless Field Effect Transistor-Reference-Cited by-同舟云学术

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Investigation of the Direct Source to Drain Tunneling in 5 nm Nanotube Junctionless Field Effect Transistor

Published:2023-04-05 Issue: Volume: Page:
ISSN:
Container-title:2023 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS)
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Author:

Gautam Pramod Kumar¹,Bharti Manisha¹,Paras Neha¹

Affiliation:

1. Nationsl Institute of Technology,ECE Department,Delhi

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10135544/10136027/10136107.pdf?arnumber=10136107

Reference29 articles.

1. Enhanced DC Performance of Junctionless Field-effect Transistor Using Dielectric Engineering

2. Optimization of Design Parameters for Vertical Tunneling Based Dual Metal Dual Gate TFET

3. Analysis of Short Channel Effects for Junction Less;dhiman;2021 International Conference on Computer Communication andInformatics (ICCCI),2021

4. A Hetero-Dielectric Double-Gate Junctionless FET with Spacer for Improved Device Performances

5. Exploiting Within-Channel Tunneling in a Nanoscale Tunnel Field-Effect Transistor

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