Optimization of Design Parameters for Vertical Tunneling Based Dual Metal Dual Gate TFET
Author:
Paras N.,Chauhan S.S.
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Investigation of the Direct Source to Drain Tunneling in 5 nm Nanotube Junctionless Field Effect Transistor;2023 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS);2023-04-05
2. Vertical Tunnel FET Technology: Optimization and Reliability Perspective;2021 International Conference on Computational Performance Evaluation (ComPE);2021-12-01