Affiliation:
1. University of British Columbia
Abstract
FPGA clock networks consume a significant amount of power, since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The efficiency of FPGA clock networks can be improved by reducing this flexibility; however, reducing the flexibility introduces stricter constraints during the clustering and placement stages of the FPGA CAD flow. These constraints can reduce the overall efficiency of the final implementation. This article examines the trade-off between the power consumption and flexibility of FPGA clock networks.
Specifically, this article makes three contributions. First, it presents a new parameterized clock-network framework for describing and comparing FPGA clock networks. Second, it describes new clock-aware placement techniques that are needed to find a legal placement satisfying the constraints imposed by the clock network. Finally, it performs an empirical study to examine the trade-off between the power consumption of the clock network and the impact of the CAD constraints for a number of different clock networks with varying amounts of flexibility.
The results show that the techniques used to produce a legal placement can have a significant influence on power and the ability of the placer to find a legal solution. On average, circuits placed using the most effective techniques dissipate 5% less overall energy and are significantly more likely to be legal than circuits placed using other techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network are up to 14.6% more energy efficient compared to other FPGAs.
Publisher
Association for Computing Machinery (ACM)
Reference21 articles.
1. ACTEL. 2007. ProASIC3 flash family FPGAs datasheet: Device architecture (Jan.). ACTEL. 2007. ProASIC3 flash family FPGAs datasheet: Device architecture (Jan.).
2. ALTERA. 2005. Stratix II Device Handbook 1. Chapter 2 (Mar.). ALTERA. 2005. Stratix II Device Handbook 1. Chapter 2 (Mar.).
3. ALTERA. 2006. Stratix III Device Handbook 1. Chapter 6 (Nov.). ALTERA. 2006. Stratix III Device Handbook 1. Chapter 6 (Nov.).
4. Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic. Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic.
Cited by
5 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Simultaneous Placement and Clock Tree Construction for Modern FPGAs;Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2019-02-20
2. UTPlaceF 2.0;ACM Transactions on Design Automation of Electronic Systems;2018-07-20
3. Stratix™ 10 High Performance Routable Clock Networks;Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2016-02-21
4. A complete dynamic power estimation model for data-paths in FPGA DSP designs;Integration;2012-03
5. Net-length-based routability-driven power-aware clustering;ACM Transactions on Reconfigurable Technology and Systems;2011-12