Stratix™ 10 High Performance Routable Clock Networks
Author:
Affiliation:
1. Altera Corporation, San Jose, CA, USA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2847263.2847279
Reference13 articles.
1. V. Betz and J. Rose "VPR: A New Packing Placement and Routing Tool for FPGA Research " in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications 1997. V. Betz and J. Rose "VPR: A New Packing Placement and Routing Tool for FPGA Research " in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications 1997.
2. J. Lamoureux and S. Wilton "Architecture and CAD for FPGA Clock Networks " in Field Programmable Logic and Applications 2006. J. Lamoureux and S. Wilton "Architecture and CAD for FPGA Clock Networks " in Field Programmable Logic and Applications 2006.
3. J. Lamoureux and S. Wilton "On the Trade-off Between Power and Flexibility of FPGA Clock Networks " 2008. J. Lamoureux and S. Wilton "On the Trade-off Between Power and Flexibility of FPGA Clock Networks " 2008.
4. Xilinx "UltraScale Architecture Clocking Resources " 24 November 2015. {Online}. Available: www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf. Xilinx "UltraScale Architecture Clocking Resources " 24 November 2015. {Online}. Available: www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf.
5. Clock skew optimization
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