Simultaneous Placement and Clock Tree Construction for Modern FPGAs
Author:
Affiliation:
1. University of Texas at Austin, Austin, TX, USA
2. Xilinx Inc., San Jose, CA, USA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3289602.3293897
Reference28 articles.
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2. Yu-Chen Chen Sheng-Yen Chen and Yao-Wen Chang. 2014. Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs. In ICCAD. 647--654. Yu-Chen Chen Sheng-Yen Chen and Yao-Wen Chang. 2014. Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs. In ICCAD. 647--654.
3. Marshall L Fisher. 1981. The Lagrangian relaxation method for solving integer programming problems. Management science Vol. 27 1 (1981) 1--18. 10.1287/mnsc.27.1.1 Marshall L Fisher. 1981. The Lagrangian relaxation method for solving integer programming problems. Management science Vol. 27 1 (1981) 1--18. 10.1287/mnsc.27.1.1
4. Xilinx UltraScale Architecture Clocking Resources User Guide. 2018. https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf . Xilinx UltraScale Architecture Clocking Resources User Guide. 2018. https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf .
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