Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization-Reference-Cited by-同舟云学术

Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization

Published:2024-02 Issue:2 Volume:43 Page:641-653
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Mai Jing¹^ORCID,Wang Jiarui¹^ORCID,Di Zhixiong²^ORCID,Lin Yibo³^ORCID

Affiliation:

1. School of Computer Science, Peking University, Beijing, China

2. School of Information Science and Technology, Southwest Jiaotong University, Chengdu, China

3. School of Integrated Circuits, Peking University, Beijing, China

Funder

Key Research and Development Program Projects of the Ministry of Science and Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Reference40 articles.

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1. A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs;2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2024-05-05