Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization
Author:
Affiliation:
1. School of Computer Science, Peking University, Beijing, China
2. School of Information Science and Technology, Southwest Jiaotong University, Chengdu, China
3. School of Integrated Circuits, Peking University, Beijing, China
Funder
Key Research and Development Program Projects of the Ministry of Science and Technology
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Link
http://xplorestaging.ieee.org/ielx7/43/10410112/10242369.pdf?arnumber=10242369
Reference40 articles.
1. FPGA placement optimization methodology survey
2. Progress and Challenges in VLSI Placement Research
3. Timing-driven partitioning-based placement for island style FPGAs
4. Routing-architecture-aware analytical placement for heterogeneous FPGAs
5. UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing
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