Routing-architecture-aware analytical placement for heterogeneous FPGAs

Author:

Chen Sheng-Yen1,Chang Yao-Wen1

Affiliation:

1. National Taiwan University, Taipei, Taiwan

Funder

Ministry of Science and Technology, Taiwan

Taiwan Semiconductor Manufacturing Company

National Science Council Taiwan

International Business Machines Corporation

SpringSoft

Genesys Logic

Academia Sinica

MediaTek

Publisher

ACM

Reference26 articles.

1. Altera Corp. http://www.altera.com. Altera Corp. http://www.altera.com.

2. Quartus II University Interface Program. http://www.altera.com/education/univ/research/quip/unv-quip.html. Quartus II University Interface Program. http://www.altera.com/education/univ/research/quip/unv-quip.html.

3. Xilinx Inc. http://www.xilinx.com/. Xilinx Inc. http://www.xilinx.com/.

4. FPGA Design Automation: A Survey

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1. AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-09

2. Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-02

3. CNN-inspired analytical global placement for large-scale heterogeneous FPGAs;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10

4. GPlace3.0;ACM Transactions on Design Automation of Electronic Systems;2018-10-18

5. GPlace;Proceedings of the 35th International Conference on Computer-Aided Design;2016-11-07

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