UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Link
http://xplorestaging.ieee.org/ielx7/43/8319545/07984833.pdf?arnumber=7984833
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1. Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-02
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3. A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration;Electronics;2023-12-20
4. An Adaptive Analytical FPGA Placement flow based on Reinforcement Learning;2023 International Conference on Microelectronics (ICM);2023-12-17
5. IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
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