A Flat Timing-Driven Placement Flow for Modern FPGAs
Author:
Affiliation:
1. University of Guelph, Guelph, Ontario
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3316781.3317743
Reference11 articles.
1. GPlace3.0
2. An Effective Timing-Driven Detailed Placement Algorithm for FPGAs
3. UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing
4. An efficient and effective analytical placer for FPGAs
5. Timing-driven placement for FPGAs
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2. Respect the Difference: Reinforcement Learning for Heterogeneous FPGA Placement;2023 International Conference on Field Programmable Technology (ICFPT);2023-12-12
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4. Detailed Placement for Dedicated LUT-Level FPGA Interconnect;ACM Transactions on Reconfigurable Technology and Systems;2022-12-09
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