An Effective Timing-Driven Detailed Placement Algorithm for FPGAs
Author:
Affiliation:
1. University of Texas at Austin, Austin, TX, USA
2. Intel, San Jose, USA
3. University of Texas at Austin, Austin, USA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3036669.3036682
Reference18 articles.
1. Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression
2. How accurately can we model timing in a placement engine?
3. Timing-driven placement for FPGAs
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2. A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs;2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2024-05-05
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4. Detailed Placement for Dedicated LUT-Level FPGA Interconnect;ACM Transactions on Reconfigurable Technology and Systems;2022-12-09
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