An Effective Timing-Driven Detailed Placement Algorithm for FPGAs
Author:
Affiliation:
1. University of Texas at Austin, Austin, TX, USA
2. Intel, San Jose, USA
3. University of Texas at Austin, Austin, USA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3036669.3036682
Reference18 articles.
1. Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression
2. How accurately can we model timing in a placement engine?
3. Timing-driven placement for FPGAs
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Detailed Placement for Dedicated LUT-Level FPGA Interconnect;ACM Transactions on Reconfigurable Technology and Systems;2022-12-09
2. Spatiotemporal Strategies for Long-Term FPGA Resource Management;2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2022-05
3. A Flat Timing-Driven Placement Flow for Modern FPGAs;Proceedings of the 56th Annual Design Automation Conference 2019;2019-06-02
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