ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration-Reference-Cited by-同舟云学术

ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration

Published:2023-02-12 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
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Author:

Shi Kan¹^ORCID,Xu Shuoxiang²^ORCID,Diao Yuhan³^ORCID,Boland David⁴^ORCID,Bao Yungang¹^ORCID

Affiliation:

1. Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China

2. ShanghaiTech University, Shanghai, China

3. Imperial College London, London, China

4. The University of Sydney, Sydney, Australia

Funder

Chinese Academy of Sciences

National Key R&D Program of China

Institute of Computing Technology, CAS

Natural Science Foundation of China

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3543622.3573187

Reference36 articles.

1. A Survey of Computer Architecture Simulation Techniques and Tools

2. Hari Angepat , Gage Eads , Christopher Craik , and Derek Chiou . 2010 . NIFD: Non-intrusive FPGA Debugger -- Debugging FPGA 'Threads' for Rapid HW/SW Systems Prototyping. 356--359. https://doi.org/10.1109/FPL.2010.77 10.1109/FPL.2010.77 Hari Angepat, Gage Eads, Christopher Craik, and Derek Chiou. 2010. NIFD: Non-intrusive FPGA Debugger -- Debugging FPGA 'Threads' for Rapid HW/SW Systems Prototyping. 356--359. https://doi.org/10.1109/FPL.2010.77

3. Feel Free to Interrupt

4. StateMover

5. Sameh Attia and Vaughn Betz. 2020. StateReveal: Enabling Checkpointing of FPGA Designs with Buried State. 206--214. https://doi.org/10.1109/ICFPT51103.2020.00036 10.1109/ICFPT51103.2020.00036

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