REMU: Enabling Cost-Effective Checkpointing and Deterministic Replay in FPGA-based Emulation-Reference-Cited by-同舟云学术

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REMU: Enabling Cost-Effective Checkpointing and Deterministic Replay in FPGA-based Emulation

Published:2023-11-06 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE 41st International Conference on Computer Design (ICCD)
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Author:

Chen Yuxiao¹,Chang Yisong¹,Zhang Ke¹,Chen Mingyu¹,Bao Yungang¹

Affiliation:

1. CAS,State Key Laboratory of Processors, Institute of Computing Technology,Beijing,China

Funder

Chinese Academy of Sciences

National Natural Science Foundation of China

Beijing Municipal Education Commission

Youth Innovation Promotion Association

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10360938/10360940/10360968.pdf?arnumber=10360968

Reference40 articles.

1. A case for FAME

2. Fast and cycle-accurate modeling of a multicore processor

3. FastLanes: An FPGA accelerated GPU microarchitecture simulator

4. A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation

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