Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices-Reference-Cited by-同舟云学术

Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices

Published:2012 Issue: Volume: Page:
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Container-title:Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures - NANOARCH '12
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Author:

Wang Yao,Cotofana Sorin D.,Fang Liang

Publisher

ACM Press

Reference16 articles.

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3. M. Alam, "A Critical Examination of the Mechanics of Dynamic NBTI for PMOSFETs," inIEEE International Electron Devices Meeting, IEDM Technical Digest, Dec. 2003, pp. 14.4.1--14.4.4.

4. A. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, and S. Krishnan, "NBTI Impact on Transistor and Circuit: Models, Mechanisms and Scaling Effects," inIEEE International Electron Devices Meeting, Dec. 2003, pp. 14.5.1--14.5.4.

5. B. Paul, K. Kang, H. Kufluoglu, M. Alam, and K. Roy, "Impact of NBTI on the Temporal Performance Degradation of Digital Circuits,"IEEE Electron Device Letters, vol. 26, no. 8, pp. 560--562, Aug. 2005.

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