1. Alam MA, Kufluoglu H, Varghese D, Mahapatra S (2007) A comprehensive model for PMOS NBTI degradation: recent progress. Microelectron Reliab 47:853–862
2. Wang Y, Cotofana SD, Fang L (2012) Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices. In: IEEE/ACM international symposium on nanoscale architectures, Published, 2012
3. Yang JB, Chen TP, Gong Y, Tan SS, Ng CM, Chan L (2010) Improvement of negative bias temperature instability by stress proximity technique. IEEE Trans Electron Devices 57:238–243
4. C.-H. Chen, T.L. Lee, T.H. Hou, C.L. Chen, C.C. Chen, J.W. Hsu, K.L. Cheng, Y.H. Chiu, H.J. Tao, Y. Jin (2004) Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65 nm high-performance strained-Si device application, In: IEEE 2004 symposium on VLSI technology. Digest of technical papers, pp 56–57
5. Yang HS, Malik R, Narasimha S, Li Y, Divakaruni R, Agnello P, Allen S, Antreasyan A, Arnold JC, Bandy K (2004) Dual stress liner for high performance sub-45 nm gate length SOI CMOS manufacturing, In: IEEE international electron devices meeting. IEDM Technical Digest, pp 1075–1077