A low-offset high-speed double-tail dual-rail dynamic latched comparator
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ACM Press
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Low Power, High Speed Improved By Dynamiclatchcomparator For Biomedical Acquisition System Using 180nm CMOS Technology;2023 First International Conference on Advances in Electrical, Electronics and Computational Intelligence (ICAEECI);2023-10-19
2. A 0.3 V 10b 3 MS/s SAR ADC with Comparator Calibration and Kickback Noise Reduction for Biomedical Applications;Analog Circuits and Signal Processing;2021-12-08
3. A novel low offset low power CMOS dynamic comparator;Analog Integrated Circuits and Signal Processing;2018-03-21
4. A 500 MHz low offset fully differential latched comparator;Analog Integrated Circuits and Signal Processing;2017-06-08
5. A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator;Analog Integrated Circuits and Signal Processing;2011-07-17
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