A Low Power, High Speed Improved By Dynamiclatchcomparator For Biomedical Acquisition System Using 180nm CMOS Technology
Author:
Affiliation:
1. Chandigarh University,Department of Computer Science and Engineering,Mohali,140413
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10370005/10370765/10370904.pdf?arnumber=10370904
Reference16 articles.
1. High-speed and low-power dynamic latch comparator
2. A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS
3. Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS
4. A low-noise self-calibrating dynamic comparator for high-speed ADCs
5. A low-offset high-speed double-tail dual-rail dynamic latched comparator
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