A novel low offset low power CMOS dynamic comparator

Author:

Gandhi Priyesh P.,Devashrayee N. M.

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Reference20 articles.

1. Baker, R. J., Li, H. W., & Boyce, D. E. (1997). CMOS circuit design, layout and simulation. In IEEE Press series on microelectronic systems, pp. 685–699.

2. Allen, P. E., & Holberg, D. R. (2002). CMOS analog circuit design (2nd ed., pp. 439–488). Oxford: Oxford University Press.

3. Sumanen, L., Waltari, M., & Halonen, K. (2000). A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters, Vol. 1. In 7th IEEE international conference on electronics, circuits and systems ICECS 2000, pp. 32–35.

4. Sumanen, L., Waltari, M., Hakkarainen, V., & Halonen, K. (2002). CMOS dynamic comparators for pipeline A/D converters. IEEE ISCAS, 5, 157–160.

5. Matthews, T. W., & Heedley, P. L. (2005). A simulation method for accurately determining DC and dynamic offset in comparators. In IEEE MWSCAS, pp. 1815–1818.

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