A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters

Author:

Sumanen L.,Waltari M.,Halonen K.

Publisher

IEEE

Cited by 25 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. A 4th-Order 4-Bit Continuous-Time ΔΣ ADC Based on Active–Passive Integrators With a Resistance Feedback DAC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-06

3. A Novel Fourth-Order Multi-Bit Quantization ΣΔ Modulator;2021 International Conference on Sensing, Measurement & Data Analytics in the era of Artificial Intelligence (ICSMD);2021-10-21

4. A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme;IEEE Access;2020

5. A novel low offset low power CMOS dynamic comparator;Analog Integrated Circuits and Signal Processing;2018-03-21

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