Author:
Vaidya Sumit,Dandekar Deepak
Publisher
Academy and Industry Research Collaboration Center (AIRCC)
Subject
Computer Networks and Communications,Hardware and Architecture
Cited by
14 articles.
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1. FPGA implementation of improved 32-bit wallace multiplier;WOMEN IN PHYSICS: 7th IUPAP International Conference on Women in Physics;2024
2. Area, Delay, and Energy-Efficient Full Dadda Multiplier;Journal of Circuits, Systems and Computers;2023-05-11
3. Efficient FPGA Implementation of RSA Algorithm Using Vedic Multiplier;2023 International Conference on Wireless Communications Signal Processing and Networking (WiSPNET);2023-03-29
4. Implementation of parallel multiplier based on Booth computing method using FPGA;2022 International Conference on Advances in Computing, Communication and Applied Informatics (ACCAI);2022-01-28
5. FPGA Implementation of 16-Bit Wallace Multiplier Using HCA;Lecture Notes in Electrical Engineering;2022