Optimize Analysis of Combined R2B, R4B and R8B FFT using Single Path Delay Feedback
Author:
Affiliation:
1. IES College of Technology,Department of Electronics and Communication Engineering,Bhopal,Madhya Pradesh,India,462044
2. IES University,Department of Computer Science and Engineering,Bhopal,Madhya Pradesh,India,462044
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10577287/10577289/10577396.pdf?arnumber=10577396
Reference20 articles.
1. Efficient ancilla-free reversible and quantum circuits for the Hidden Weighted Bit function
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3. A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G
4. Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data
5. Implementation of Vedic multiplier for Digital Signal Processing;Kerur
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