4×4 Array Multiplier Using Transmission Gate Full Adder-Reference-Cited by-同舟云学术

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4×4 Array Multiplier Using Transmission Gate Full Adder

Published:2024-04-05 Issue: Volume:8 Page:1-7
ISSN:
Container-title:2024 IEEE 9th International Conference for Convergence in Technology (I2CT)
language:
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Author:

Rathore Nitesh Kumar¹,Beohar Ankur²,Sarkar Pallabi²,Khare Kavita³,Singh Pooran¹

Affiliation:

1. Mahindra University,Dept. of Electrical and Computer Engineering,Hyderabad,India

2. VIT Bhopal University,School of Electrical and Electronics Engineering (SEEE),Madhya Pradesh,India

3. MANIT Bhopal,Dept. of Electronic and Communication Engineering,Madhya Pradesh,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10543249/10543223/10543507.pdf?arnumber=10543507

Reference15 articles.

1. Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation

2. Study of Low Power Array Multiplier for Real Time Applications;Patil;International Journal of Research and Advanced Development (IJRAD).

3. Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process

4. Low power array multiplier using modified full adder

5. Comparison of a 32-bit Vedic multiplier with a conventional binary multiplier

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