Author:
Bisoyi Abhyarthana,Baral Mitu,Senapati Manoja Kumar
Cited by
18 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. High Speed 64 Bit Vedic & Booth Multiplier Implementation Using FPGA;2024 3rd International Conference on Artificial Intelligence For Internet of Things (AIIoT);2024-05-03
2. 4×4 Array Multiplier Using Transmission Gate Full Adder;2024 IEEE 9th International Conference for Convergence in Technology (I2CT);2024-04-05
3. A novel reversible gate and optimised implementation of half adder, subtractor and 2-bit multiplier;Analog Integrated Circuits and Signal Processing;2023-12-24
4. Low Power Performance Analysis of 16-Bit Vedic Math RISC Processor;2023 3rd Asian Conference on Innovation in Technology (ASIANCON);2023-08-25
5. Design of 32-bit RISC V using area efficient multiplier based on homogeneous hybrid adder;INTELLIGENT BIOTECHNOLOGIES OF NATURAL AND SYNTHETIC BIOLOGICALLY ACTIVE SUBSTANCES: XIV Narochanskie Readings;2023