VLSI Architecture for Reversible Radix-2 FFT using Modified Carry Select Adder-Reference-Cited by-同舟云学术

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VLSI Architecture for Reversible Radix-2 FFT using Modified Carry Select Adder

Published:2024-04-23 Issue: Volume: Page:102-106
ISSN:
Container-title:2024 7th International Conference on Devices, Circuits and Systems (ICDCS)
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Author:

Ranjan Abhay Kumar¹,Singh Ompal¹,Nemade Sandip²

Affiliation:

1. TIT,Department of ECE,Bhopal

2. Department of ECE,Bhopal

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10560478/10560483/10560751.pdf?arnumber=10560751

Reference15 articles.

1. Efficient ancilla-free reversible and quantum circuits for the Hidden Weighted Bit function

2. Area efficient VLSI architecture for reversible radix_2 FFT algorithm

3. A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G

4. Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

5. Implementation of Vedic multiplier for Digital Signal Processing;Kerur

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