Ultra-low power 1T-DRAM in FDSOI technology

Author:

El Dirani H.,Lee K.H.,Parihar M.S.,Lacord J.,Martinie S.,Barbe J-Ch.,Mescot X.,Fonteneau P.,Broquin J.-E.,Ghibaudo G.,Galy Ph.,Gamiz F.,Taur Y.,Kim Y.-T.,Cristoloveanu S.,Bawedin M.

Funder

EU project

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference22 articles.

1. A capacitor-less 1T-DRAM cell;Okhonin;IEEE Electron Device Lett.,2002

2. A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications;Kuo;IEEE Trans. Electron Devices,2003

3. New generation of Z-RAM;Okhonin,2007

4. A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory;Yoshida;IEEE Trans. Electron Devices,2006

5. Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SO1 to double-gate FinDRAM;Tanaka,2004

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3. Micro-features of ambipolar snapback behaviour under high current injection to design capacitorless memory device;Physica Scripta;2021-12-01

4. Band-modulation devices;Fully Depleted Silicon-On-insulator;2021

5. Suppressing crosstalk in the photoelectron in-situ sensing device (PISD) by double SOI;2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS);2020-09-01

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