Micro-features of ambipolar snapback behaviour under high current injection to design capacitorless memory device

Abstract

Abstract This paper presents micro-features of capacitorless memory cells based on snapback phenomenon and modeling of space-charges. 2—Dimensional gate grounded NMOS structure is specified and its operational window of the memory cell is inspected using the Synopsys TCAD tool. This work examines snapback behaviour in one transistor DRAM memory cell in the absence of a storage capacitor under zero gate bias and applied ramp of high current at the drain terminal. Carrier electrostatics and memory cell mechanisms are also explored by adjusting the slope of the high current ramp. The process variation is examined for different parameters in the device. The current crowding phenomenon due to the injection of electrons and holes is investigated, giving rise to ambipolar behaviour. Due to the snapback, redistribution of electron and hole current is investigated. This work also evaluates the impact on electrostatic potential along channel and bulk under the snapback. It explains the dependency of snapback on potential build-up. Post-snapback electron current flipping presents the flow line near the gate region. The bipolar activity is manifested in surface and bulk regions to show its impact through analytics. The effect of gate biasing is also examined under the applied current ramp.