1. A 14 nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm 2 SRAM cell size;Natarajan,2014
2. A 0.034 mm 2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8–19.3 GHz transformer-based fractional-N all-digital PLL in 10 nm FinFET CMOS;Natarajan;Proc. IEEE VLSI,2016
3. Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications;Cho,2016
4. Bottom oxidation through STI (BOTS) - a novel approach to abricate dielectric isolated FinFETs on bulk substrates;Cheng,2014
5. FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin;Zhang,2016