Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

Abstract

In this paper, in order to improve the driving ability of vertically-stacked gate-all-around (GAA) Si nanosheets (NSs) devices, a high-efficiency hybrid pattern technique with the SiNx spacer-image transfer (SIT) and conventional photolithography pattern was proposed and implemented to form size-enlarged landing pads (LPs) on nanscale fins at the same time, which increase the volumes of electrical conductance pathway between NS channels and source and drain (SD) electrodes with high process efficiency and compatibility with traditional mass production technology. Due to introduced new structures, the parasitic resistance of the devices is reduced by 99.8% compared with those of w./o. LPs. Therefore, ∼3 times and ∼2 times driving current enhancements for 500 nm gate length n-type and p-type MOSFETs are obtained, respectively. The results indicate the proposed GAA NS FET fabrication process with LPs by high-efficiency hybrid pattern technique a promising solution for improving the device driving ability for stacked GAA Si NSs devices in future.